Electrical and Electronics

OFDM systems are widely used in both wired and wireless communication systems. Fast Fourier Transform is one of the key processing in the implementation of OFDM systems such as wireless broadband, and ultra wideband systems. In most researches, the implementation of Fast Fourier Transform is focused on reducing the difficulties in multipliers, memory unit and control circuits involved in the FFT process. Modification in the architecture for pipelined FFT processor is proposed, to reduce the register size required for FFT processor. In OFDM, this FFT process is used at the receiver side of the system. The single-path delay-feedback architecture is used to exploit the spatial regularity in signal flow graph of the algorithm.

Super-resolution is the process of creating an high resolution image from a low resolution input sequence. To overcome the difficulties of good image registration, several methods have been proposed exploiting the non-neighbourhood intuition, i.e. any data-point can contribute to the ?nal result if it is relevant. These algorithms however limit in practice the search region for relevant points in order to lower the corresponding computational cost. Furthermore, they de?ne the non-neighbourhood relations in the high resolution space, where the true images are unknown. In this work, we introduce the use of phantom hashing to efficiently compute fully non-neighbourhood neighbours. We also restate the super-resolution functional using ?xed weights in the low resolution space, allowing us to use resolution schemes that avoid many artifacts.

In recent years energy generation from renewable sources in clean, efficient and environment friendly manner is a real challenge. Among the various non conventional sources, photovoltaic(PV) generation using multilevel inverter topologies are widely used due to the economy of use, flexibility in control under partially shaded conditions and the high quality of voltage waveforms. This work focuses on a single phase nine level cascaded inverter using PIC16F877A microcontroller to generate the required gate signals. The notch angles for the gate signals are calculated using selective harmonic elimination method. Using this method the total harmonic distortion is minimized by eliminating the most significant low frequency harmonic components from the voltage waveforms. The high frequency harmonic components can then be easily eliminated using additional filter circuits. The entire setup has been simulated in MATLAB and verified using the hardware setup.

The synchronization of the chaotic sequence using open plus closed loop (OPCL) coupling is presented in this paper by realizing 1D logistic map in microcontroller based hardware electronic experiment. The masking of the information signal in driver and demasking in the driven system is done in the chaotic region by using two microcontrollers ATMEGA 16 for secure communication. These two microcontrollers are used for driver and driven systems. In the synchronized condition driver system received the modulating signal from the signal generator and mask it with the chaotic sequence for transmitting to the driven system. In the receiver, section demasking is done to retrieve the information signal. The proposed scheme is simulated in Proteus simulator and the complete hardware circuit has been implemented and the obtained hardware experimental results confirm the validity of the proposed circuit.

A novel RF-MOSFET (Radio Frequency Metal Oxide Semiconductor Field Effect Transistor) model with PTM (Predictive technology model) for 90 nm CMOS (Complementary Metal Oxide Semiconductor) technology is presented. A simple and accuracy method is developed to directly extract all the high frequency parasitic effect from measured S-parameter biased at zero and linear region. This model is proposed to overcome some of short channel effects at nano-scale highly dopped drain and source based on the conventional small signal MOSFET (Metal Oxide Semiconductor Field Effect Transistor) equivalent circuit, RF (Radio Frequency) characterization of CMOS (Complementary Metal Oxide Semiconductor) has been taken up in terms of RF Figure of Merits. The excellent correspondence is achieved between simulated and measured S-parameter (Scattering parameter) from 1GHz to 10 GHz frequency range.

This paper presents the design style and analysis of ultra-low power digital system using reversible logic. Adiabatic technique is the one which uses reversible logic for low power system, this technique is implemented for the digital systems 4-bit, 8-bit adder-subtractors and also 3-bit, 5-bit BEC (binary to excess-1 converter) based on ECRL (Efficient Charge Recovery Logic) and PFAL (Positive Feedback Adiabatic Logic) logic families which works with the professional four phase power clock. These styles have the profit of energy saving as it reuse the certain amount of the energy by recycling from the load capacitance thus reduces the energy dissipation. MOS level-11 Tanner-spice simulation has been used for the design of Energy saving adiabatic circuits with consideration to particular frequencies with the different load capacitance, and different supply voltages. In analysis, two logic families, ECRL (Efficient Charge Recovery Logic) and PFAL (Positive Feedback Adiabatic Logic) are compare with conventional CMOS logic for Incrementors and adders. Also comparison of ECRL (Efficient Charge Recovery Logic) and PFAL (Positive Feedback Adiabatic Logic) is done. In the analysis it has found that adiabatic is superior for low power applications in Cryptographic hardware for example smart cards, Digital Signal processing system and embedded systems at particular frequency choice.

This paper emphasis the automatic remote EB metering system using the existing GSM technology to reduce the human intervention, in order to save invaluable man time and to reduce the cost. This is fast, accurate and time saving. Though both analog and digital meters are widely used, in this work the existing analog reading meter with additional circuitry of IR sensor is used for demonstration. Nowadays GSM network is not only used mere mobile conversation, its applications are countless. At the end of every month or the date programmed in the controller, the actual readings (units consumed) will be sent to the consumer by the SMS (Short Messaging Services). ARM microcontroller has been programmed to govern all these works. A prototype system has been developed for experimentation.

This paper discusses the ways for maintaining high availability of a system in order to keep high reliability figure. In doing so, the basic principles of reliability are discussed. Since good maintenance practice enhances availability, some important topics on maintenance management are also discussed. At the end recommendations are made on how to keep a system in a high availability state.

Positioning of nodes in ad hoc networks of vehicles in recent years is an interesting subject for research, helps to build the topologic map for car. It also provides information about places close to the car. For the open wireless communication and mobility with high -speed for a large number of vehicles, in inter- vehicle communication, authentication message, integrity and privacy of the car have been identified as the main security requirements. In this study, methods for vehicle location privacy is proposed, which include: define a switch pair and a number alias for vehicles, vehicle grouping,, select the leader for groups and finally use of several RSUs. At the end of the study, the proposed method is simulated using NS2 software, and some critical parameters of the network, are examined to see the effect of the proposed method on the network.

Differential Power Analysis (DPA) has been shown to be an effective attack in cryptographic systems capable of revealing secret data by measuring power consumption. Recent DPA resistant circuits / logics incur severe penalties in terms of area and power. This paper proposes the design of a secure logic family for DPA resistant cryptographic devices. Here the power consumption is insensitive to unbalanced load conditions thus adopting a semi-custom design flow without any constraint on the routing of the complementary wires. The proposed logic is based on a novel encoding concept where the information is represented in time domain rather than in the spatial domain as in standard dual-rail logic. In this paper, a logic family exploiting the proposed concept is simulated to show power consumption independent of the processed data and routing capacitances. It also shows an optimistic improvement in the energy consumption balancing and area reduction.