Condensed Matter

Sodium Nitrite is an example of crystal that were found to be ferroelectric a number of years after the discovery of their phase transitions. A change from a non-centrosymmetric to a centric structure is known to occur in NaNO2 at approximately 160 °C. This transition was discovered to be a ferroelectric in 1958. Above the Curie point, the structure is orthorhombic with lattice constants at 205 °C and space group Immm. The dielectric constant exhibits a sharp anomaly at the Curie point and obeys the Curie-Weiss law. The transition is obviously one of the first order. The spontaneous polarization is rather large, namely of the same order as that of KNO3. At 143 °C, Ps = 6.4x10-6 C/cm2, and the 50 c/s coercive field Ec = 2.3 kV/cm. The coercive field is is so large, at room temperature that hysteresis loops cannot be obtained with fields of the order of 25 kV/cm. Above the Curie point, these ions may oscillate along the [010] axis about positions which can be described in terms of the centrosymmetrical space group Immm, but there are also indications that this centric symmetry may be the result of random disorder.

Noise is defined as any unintended signal that interferes with circuit operation. Although this includes spurious signals of human origin or the external environment, this investigation is limited to noise that result from microscopic fluctuations within the semi-conductor components of the circuit. While noise is typically seen as an analog circuits problem, it is believed that noise will become of greater concern in digital circuits as devices shrink, power supply voltages are reduced, and the number of carriers conducted by these devices is reduced. Noise under large-signal conditions is an important consideration in the design of wireless communications circuits. It has an effect on the spectral purity of oscillators and the noise figure of mixers and power amplifiers. The ability to simulate the noise of LC Voltage- Controlled Oscillators (VCOs) makes it possible to predict their performance in these types of circuits. It is then possible to have a better picture of the worst-case performance of these circuits so that overdesign or costly redesigns are not necessary. This paper presents the development and simulation techniques and mathematically accurate models at the component level resulting in optimization of low frequency loading, feedback circuit and emitter degeneration which can help minimize the phase noise in FET oscillators subject to design constraints such as power dissipation, tank amplitude, tuning range, start-up condition, and diameter of spiral inductors.VCO output frequency is tuned by on-chip p /n-well junction varactors. The circuit topology minimizes the amount of fixed parasitic capacitance in the tank circuit. The simulation results show that the proposed VCO can reach the frequency wished to the telecommunication application. Parameters from an industrial0.35 ?m CMOS process are used for simulations. The nominal operating frequency of these oscillators is 2.4 GHz. They are designed to be resistant to supply and temperature effects. This oscillator achieves the necessary temperature and supply independence while being tunable about 2.4 GHz. Using only 2.5V of power supply and 1V of tuned voltage, the circuit shows a simulated single-output sensitivity of 565ppm/°C at 27C temperature and -0.47%/Volt at 2V.

Chalcogenide based semiconductors have attracted much attention recently due to their applications in solid state devices (SSD). Chalcogenide phase change memory is considered as a potential replacement of flash memory due to its high storage density and archival stability. Phase change non-volatile semiconductor memory technology is based on an electrically initiated, reversible rapid amorphous-to-crystalline phase change process in multicomponent chalcogenide alloy materials similar to those used in rewritable optical disks. In order to view the suitability of a material for PRAM applications, it is necessary to investigate the crystallization behaviour of the material concerned. In the present work, a systematic investigation of crystallization kinetics of In40Se60 alloy has been made. Thin films of In40Se60 alloy were prepared by thermal evaporation using Edward Auto 306 evaporation system. Electrical measurements at room temperature and upon annealing at different heating rates were done by four point probe method using Keithley 2400 source meter interfaced with computer using LabView software. The dependence of sheet resistance on temperature showed a sudden drop in resistance at a specific temperature corresponding to the transition temperature at which the alloy change from amorphous to crystalline. The transition temperature was also found to increase with the heating rates. From the heating rate dependence of peak crystallization temperature (Tp) the activation energy for crystallization was determined using the Kissinger analysis. The films were found to have an electrical contrast of about six orders of magnitude between the as-deposited and the annealed states, a good quality for PRAM applications. The activation energy was determined to be 0.538±0.063eV.